Lead Interconnect Architect, RISC-V/TileLink (Chisel)

SiFive is seeking a principal-level hardware engineer to drive the design of industry-leading CPU and interconnect IP for RISC-V SOCs. You will develop configurable hardware generators using Chisel and FIRRTL, enabling rapid, software-like iteration and high-quality hardware blocks.

Responsibilities include advancing TileLink interconnects, cache controllers and bridges, while ensuring high performance and scalable coherence across multi-core systems.

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