Principal Digital RTL Engineer — SoC & Silicon Impact

Cadence Design Systems in Edinburgh, UK, seeks a Principal Digital Design Engineer to drive high-performance RTL development for advanced SoCs within the PSG. You will own RTL from architectural concepts through synthesis and handoff, collaborating with architecture, verification, and physical design teams to solve complex silicon problems.

The role targets senior engineers with expertise in SystemVerilog, RTL debugging, and timing closure, contributing to cutting-edge semiconductor solutions

#J-18808-Ljbffr