Principal FPGA Design Engineer

Renishaw’s Encoder Products Division (EPD) designs and supplies cutting-edge position feedback technology to the world’s precision measurement, automation, and manufacturing industries. It is highly likely that something you own contains a part or device that was manufactured with the help of one of Renishaw’s encoder products.

EPD is made up of engineers, scientists and technicians all working together to produce market leading products for sale around the world. We start with cutting edge optical, algorithm and circuit design, developing our own ASICs and sensors where required; we then use innovative mechanical engineering to turn our core technology into a range of desirable products for our broad customer base.

Working closely with colleagues in our manufacturing division, we develop manufacturing and assembly processes and software to deliver quality products by the hundreds of thousands that in turn, perform reliably and repeatedly to sub-micron accuracies for our customers.

A position has become available for a Lead FPGA Design Engineer to join a talented multi-disciplined team at the forefront of new product design and research and development projects.

We’re looking for a Lead FPGA Engineer to take technical ownership of the FPGA designs in our encoder products. This is a hands‑on role combining architecture and delivery leadership with day‑to‑day FPGA development, debugging and verification in simulation and on real hardware.

The FPGA often works alongside MCU and analogue electronics; a sound appreciation of all aspects of high-speed design (both analogue and digital) is essential. For certain product lines, you will also contribute to development practices and evidence that support functional safety certification.

You’ll work closely with systems, electronics, algorithms, software, and test teams - and you’ll play a key role in mentoring graduates and apprentices, helping the team deliver reliably while developing capability.

Responsibilities

• Drive the development of new precision measurement products, working with project managers and product managers to define agreed product specifications and deliver designs to meet those specifications and which are suitable for transfer to production.
• Lead, develop and maintain FPGA architecture and design from early prototypes through to production and long-term support.
• Lead and develop reusable VHDL code with a focus on optimisation minimal resource usage, reliability and portability to different FPGA families
• Lead and develop reusable testbench VHDL using OSVMM to achieve high verification coverage
• Understand, evaluate, and implement embedded algorithms on FPGA targets with a focus on performance, accuracy, determinism, numerical robustness, and repeatable behaviour.
• Set engineering direction and maintain high standards through design reviews, code reviews, coding standards, and pragmatic best practice adoption.
• Drive the capture, refinement, and traceability of requirements - working closely with systems, electronics, algorithms, FPGA/RTL, and test teams - translating high‑level user expectations into implementable firmware requirements and verifiable behaviour.
• Support functional safety certification where required, contributing to safety lifecycle activities such as safety requirements, design constraints, traceability, verification planning, and producing audit‑quality evidence.
• Produce and maintain clear documentation: architecture, interfaces, design rationale, timing/power budgets, verification approach, and support notes suitable for long‑term product maintenance.
• Mentor and support engineers, especially graduates/apprentices: create well‑scoped work packages, provide guidance and review, and help maintain delivery momentum despite high junior‑engineer rotation.
• Work within a multi‑disciplined team to assist with the optimisation and the interaction between Electronic, Mechanical and Software components in all designs, whilst gaining an appreciation of metrology (the science of measurement)

Key requirements

• Degree in electronic engineering, physics or similar
• Solid experience in FPGA design lifecycle including:
• VHDL or Verilog RTL development - ideally including recent experience with Altera (Intel), Lattice or AMD (Xilinx) FPGAs.
• VHDL or Verilog verification (e.g. OSVVM) including continuous integration techniques.
• Implementation and verification of FPGA designs on hardware.
• Design for ruse - RTL and testbench
• Detailed understanding of FPGA devices and how to write VHDL for optimisation of resources and to achieve timing closure
• Solid understanding of timing constraints
• Solid understanding of digital design, logic timing, clock domain crossings, pipelining.
• Practical understanding of microcontrollers, embedded software and signal processing techniques
• Knowledge of C, C++, assembly language or other embedded software languages
• Experience of OSVVM, VUnit, Aldec ActiveHDL, Matlab, Python, Git Version control, Azure DevOps
• Demonstrable expertise in electronic design including high speed, low power circuits and electromagnetic compatibility; capable in both analogue and digital domains
• Knowledge and experience of safety and reliability standards including IEC 61508 and ISO 13849

Person specification

You are a technically strong Engineer with an excellent understanding FPGA design fundamentals and an enquiring mind, who leads by example and thrives in multidisciplinary environments. You are comfortable working at the boundary between the FPGA and the wider system, and you can understand and collaborate across electronics, software/firmware, mechanics, and optics to shape system architecture and translate user expectations into robust, testable requirements.

You take ownership of complex problems, communicate clearly, and maintain a high bar for engineering quality. You are also motivated to develop others: you can mentor graduates and apprentices effectively, break down work into well‑scoped packages that fit varied experience levels and time horizons, and keep delivery on track even with the regular rotation of early‑career engineers.

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