Principal Interconnect IP Design Engineer (RISC‑V/TileLink)

SiFive is seeking a principal‑level hardware engineer to design industry‑leading CPU and interconnect IP, driving RISC‑V adoption across SOC designs. You will build highly configurable hardware generators using Chisel/Scala and integrate them into SiFive’s Chisel/FIRRTL workflow.

The role emphasizes scalable IP design, fast time‑to‑market, and collaboration across verification and design teams to deliver high‑quality, performant solutions.

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