RISC-V CPU RTL Architect & Microarchitecture Engineer

SiFive in Cambridge, United Kingdom, is seeking a CPU Microarchitecture/RTL design engineer to help build industry-leading RISC‑V cores. You will design features, implement ISA extensions, and advance Chisel-based workflows across the development stack.

You will verify designs, collaborate with verification, physical design, and performance teams, and contribute to documentation and reusable test content in a fast-paced, collaborative environment.

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