Senior FPGA Engineer – Compute Architecture & Hardware Acceleration

Excellent opportunity for a Senior FPGA Engineer – Compute Architecture & Hardware Acceleration to join an innovative technology business on a hybrid basis, with time spent at their Oxford site, helping develop next-generation probabilistic computing platforms and advanced hardware acceleration solutions. This role will require expertise in FPGA design, algorithm implementation, and high-speed digital systems development.

Key responsibilities for the Senior FPGA Engineer – Compute Architecture & Hardware Acceleration role (hybrid and Oxford based):

• Translate complex probabilistic algorithms from Python, C++, MATLAB and pseudocode into highly pipelined, resource-efficient FPGA RTL designs
• Design and implement custom digital logic in VHDL from scratch where vendor IP is unsuitable, introduces latency or creates bottlenecks
• Architect and integrate high-speed data acquisition pipelines utilising ultra-fast ADCs, PCIe, high-speed Ethernet and transceiver technologies
• Work closely with hardware engineers, software developers, researchers and ASIC architects to define system architecture and technical solutions
• Develop robust verification environments, perform hardware bring-up activities and optimise timing, power and resource utilisation across multiple clock domains

Key skills required for the Senior FPGA Engineer – Compute Architecture & Hardware Acceleration role:

• Degree in Electrical Engineering, Computer Engineering or a related discipline
• Demonstrable experience of FPGA digital design experience developing complex, high-speed digital systems
• Strong HDL expertise with a proven ability to develop custom RTL from scratch
• Experience with FPGA SoC platforms, including practical knowledge of processor-side development and PS/PL architectures such as Zynq
• Proven ability to translate mathematical or algorithmic models into hardware accelerators using fixed-point arithmetic and bit-accurate modelling techniques
• Strong understanding of timing closure, clock domain crossing (CDC) and advanced digital design principles
• Experience with Xilinx Vivado, Vitis and TCL scripting toolchains
• Familiarity with hardware debugging tools including oscilloscopes, logic analysers, JTAG debuggers and signal generators

This is an opportunity to work at the forefront of probabilistic computing, helping define the hardware architecture for a revolutionary computing platform while collaborating with leading experts and researchers in the field.

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