Senior RTL Design Engineer — RISC-V Core Architect

SiFive is seeking a qualified engineer to architect, design, and implement features and ISA extensions in RISC-V CPU core generators using Chisel. You will integrate content into the FIRRTL framework and help automate documentation, verification tests, and packaged software.

You will verify designs with the verification team and work with physical implementation to optimize for frequency, area, and power. The role requires 3+ years of design experience, proficiency in Verilog/SystemVerilog/VHDL,

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