Senior SoC Physical Design Engineer — Power and Timing

Analog Devices is seeking a Senior Physical Design Engineer to own the physical implementation of complex mixed-signal SoCs for the Data Center & Energy group. The role spans floorplanning, power planning, placement, clock tree synthesis, routing, and timing closure across multiple process nodes.

Collaboration with RTL, analog layout, and verification teams is essential to deliver silicon meeting performance, power, and area targets.

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