Senior Verification Architect for 100Gbps Networking IP

Oriole Networks is seeking an experienced Verification Engineer to design and implement high-performance verification for FPGA/ASIC interfaces at 100Gbps+ speeds. You will build testbenches, develop tests, and drive coverage closure across module and system levels.

You will collaborate closely with RTL and hardware teams, applying advanced verification methodologies and tools (SystemVerilog, TCL, Python) to deliver robust, production-grade IP and interfaces.

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