Senior Verification Engineer

Overview

Fractile’s mission is to enable a new chapter in the AI revolution. We’re pioneering AI innovation where hardware and software join to create something truly extraordinary, unlocking the power of the world’s largest language models with speed increases of x100. Our team is rapidly expanding, and we're searching for visionary engineers, scientists, and thinkers who share our passion for pushing boundaries and redefining what's possible. If you're ready to join a dynamic group of innovators shaping AI's future, we want to hear from you!

As a Silicon Verification Engineer, you will be reporting to the Director of Frontend Silicon, and will be based in either our Bristol or London office in the UK. We are looking for you to take an active role in building world-class ML/AI IC products for scale-out to data centre applications. You will be ambitious and have a proven track record in working in high-performance delivery organisations in the discipline of pre-silicon RTL verification.

We are looking for someone who is passionate about verification – not someone content to go through the motions, but rather looking to push the field further forwards. If you get excited about bringing software concepts to hardware workflows, and enjoy improving established practices to increase tape-out quality and bring down costs, then this is the role for you.

Our preferred candidate will be comfortable working alongside colleagues across the organisation from disciplines such as modelling, system architecture and RTL design. You’ll be frequently collaborating to ensure our RTL releases are of the highest functional quality, and that the entire company shares the same definition of a functionally correct product. This means contributing to discussions around specification, architecture and the workflows surrounding them. You’ll be a key contributor to our highly disruptive and ambitious product.

We look for engineers with the following mindset:

• Software mindset for solving hardware problems
• The desire to be in a high impact role in a small team
• A disrupter of the “status quo” of hardware development
• Eagerness to contribute to and improve working practices and help build connections between hardware and software teams
• Detail-focused, with rigour as the baseline for all work
• Humility, desire to learn
• Happy to be part of a fast-paced, open and collaborative environment

Required skills and experience:

• Verification planning and execution from specification
• Building testbenches
• Functional modelling of hardware blocks
• Checker creation
• Strong software skills
• Python preferred, other languages acceptable

Understanding of digital hardware concepts

Ability to read and debug RTL in SystemVerilog

Familiarity with debugging waveforms

Desirable skills and experience:

• Whether in UVM, SystemC or another methodology
• SystemVerilog Assertions (SVA)
• Software fluency in multiple languages
• Open source tools for silicon development
• Cocotb (used for all our testbench collateral), Verilator, Icarus Verilog

Commercial EDA tools

Formal verification

Bazel is our chosen tool, familiarity is not expected

Contributing to architecture discussions

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