Space Avionics FPGA Engineer (RTL & Testing)

EVONA is seeking an avionics FPGA engineer to lead RTL design and verification across the full development lifecycle for space systems. The role involves hands-on work from RTL design and simulation to hardware testing and flight readiness.

Ideal candidates will have SystemVerilog/Verilog experience, proficiency in clock-domain crossings, timing analysis, and timing closure, plus SerDes and memory interfaces.

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