Ultra-Low Latency C++ Lead with FPGA Acceleration

JPMorgan Chase is seeking an Ultra Low Latency C++ Lead Software Engineer within the Electronic Trading Technology team in London. You will design, build, and operate market gateway solutions with FPGA acceleration, driving stability, latency optimization, and regulatory compliance.

You will partner with hardware teams to integrate FPGA pipelines with a high-performance C++ stack, affecting trading connectivity and risk management applications used globally.

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